Espressif Systems /ESP32-S3-ULP /RTC_CNTL /RTC_COCPU_CTRL

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Interpret as RTC_COCPU_CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (COCPU_CLK_FO)COCPU_CLK_FO 0COCPU_START_2_RESET_DIS 0COCPU_START_2_INTR_EN 0 (COCPU_SHUT)COCPU_SHUT 0COCPU_SHUT_2_CLK_DIS 0 (COCPU_SHUT_RESET_EN)COCPU_SHUT_RESET_EN 0 (COCPU_SEL)COCPU_SEL 0 (COCPU_DONE_FORCE)COCPU_DONE_FORCE 0 (COCPU_DONE)COCPU_DONE 0 (COCPU_SW_INT_TRIGGER)COCPU_SW_INT_TRIGGER 0 (COCPU_CLKGATE_EN)COCPU_CLKGATE_EN

Description

configure ulp-riscv

Fields

COCPU_CLK_FO

cocpu clk force on

COCPU_START_2_RESET_DIS

time from start cocpu to pull down reset

COCPU_START_2_INTR_EN

time from start cocpu to give start interrupt

COCPU_SHUT

to shut cocpu

COCPU_SHUT_2_CLK_DIS

time from shut cocpu to disable clk

COCPU_SHUT_RESET_EN

to reset cocpu

COCPU_SEL

1: old ULP 0: new riscV

COCPU_DONE_FORCE

1: select riscv done 0: select ulp done

COCPU_DONE

done signal used by riscv to control timer.

COCPU_SW_INT_TRIGGER

trigger cocpu register interrupt

COCPU_CLKGATE_EN

open ulp-riscv clk gate

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